1. Field of the Invention
The present invention relates to a method of manufacturing metal-oxide-semiconductor (MOS) components, and more particularly to a method of manufacturing MOS components having a lightly doped drain structure formed by using different ionic types in the implementation process.
2. Description of Related Art
MOS components are becoming smaller and smaller in order to increase the level of integration and speed of operation, therefore, the channel length of such components is being correspondingly reduced. As a consequence of the shortening of the channel length of a MOS transistor, detrimental short channel and hot electron effects have become dominant. To alleviate the problems caused by a reduction in channel length, it is common practice to add a group of impurity diffusion regions with dopant concentration level less than that of the original source/drain regions in areas surrounding the channel inside the original source/drain regions. This structural layout is known as a lightly doped drain (LDD).
FIGS. 1A through 1D show the manufacturing of an MOS component having a lightly doped drain structure. Referring to FIG. 1A, a substrate 10, such as a P-type silicon substrate, is provided having a plurality of gates 11 and field oxide layers 12 defined over it. Using the gates 11 and the field oxide layers 12 as masks, N-type ions, such as phosphorus ions, having a moderate concentration of about 10.sup.13 /cm.sup.2 are implanted into the substrate 10 forming lightly doped drain regions 13.
Referring next to FIG. 1B, spacers 14 are formed on the sidewalls of the gates 11. The spacers 14 can be made from material such as silicon dioxide or silicon nitride. The spacers 14, beside serving as partitions for separating adjacent gates 11, further function as masks with gates 11 when the source/drain regions are undergoing heavy doping.
Referring next to FIG. 1C, using the gates 11, the spacers 14, and the field oxide layers 12 as masks, N-type ions such as arsenic ions, having a concentration level of about 10.sup.15 /cm.sup.2 and deep implantation depth levels, are implanted into the substrate 10 forming the source drain regions 15.
Thereafter, referring to FIG. 1D, a planarized insulating layer 16 made from material such as borophosphosilicate glass (BPSG) is formed over the surfaces of the aforementioned layers. Next, a pattern is defined on the insulating layer 16 thereby forming contact window openings 17 that expose the source/drain regions 15. Finally, a conducting layer 18, such as an aluminum layer, is formed in the contact window openings 17 to form a plurality of contact windows 18.
In the above described conventional manufacturing process for forming a lightly doped drain structures of an MOS component, the spacers 14 are required to function as masks in the process of doping the source/drain regions 15 after the formation of the lightly doped drain regions 13. Moreover, because of the presence of spacers 14 on two sidewalls of the gate 11 and the thickness of the insulating layer 16, the available area for the contact window openings 17 is reduced, thereby lowering the contact surface area with the source/drain regions 15. This reduction in contact surface area results in increased resistance and a lowering the level of integration between the source/drain regions 15 and the conducting layer 18.